Standby power is electric power that is consumed by electronics when they are in, for example, a sleep mode, a hibernate mode, or a standby mode. Although an electronic device may appear (at its interface) to be turned off, the electronic device is not necessarily disconnected from a corresponding power supply for driving the microprocessor of the electronic device. The power supply in hibernate/standby mode is suitable to preserve the volatile electronic charge states in a microprocessor. If power is disconnected, all the stored states (in terms of volatile electronic charges) should be off-loaded to main memory, and should be fed back to the microprocessor at wake up, which is an expensive and time-consuming process that is not preferred. Accordingly, power supply is lowered to a voltage Vccmin (e.g., a minimum voltage in the range of 0.4V to 0.7V that can be achieved without disturbing electronic charge states), and standby power is used by the electronic device while the electronic device is in standby mode, and is therefore not performing its primary function, such that the electronic device may be activated by a corresponding signal to switch from standby mode.
Overall chip leakage is severely limited by leaky, high performance, low threshold voltage devices within the electronic device. As feature sizes of electronic devices continue to scale, transistors within the electronic devices are scaling as well, thereby increasing leakage current associated with the standby mode. Accordingly, different methods and circuit configurations may be used to reduce overall leakage of the electronic device.
A popular technique to reduce leakage is referred to as “power gating.” Power gating is a technique used in integrated circuit design that reduces power consumption by inserting a low leakage transistor at a circuit block of leaky transistors.
For example, power gating may use transistors, such as n-channel metal-oxide-semiconductor field-effect transistors (NMOS transistors), as footer switches to effectively lower the leakage current flowing through a power gated block/circuit when the block/circuit is in standby mode. That is, an NMOS transistor may be placed between the circuit block of CMOS transistors and ground as a footer switch, with the footer switch enabled during sleep mode.